1. Field of the Invention
The present invention relates generally to an apparatus and a method for synchronizing a channel card in a mobile communication system. More particularly, the present invention relates to an apparatus and a method for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a channel card, and for synchronizing a plurality of channel cards.
2. Description of the Related Art
In conventional mobile communication systems, a base station uses a channel card to generate signals to be sent to a terminal or to recover signals received from the terminal. For instance, in an Orthogonal Frequency Division Multiplexing (OFDM) wireless communication system, the channel card generates or recovers OFDM signals. The channel card of a Code Division Multiple Access (CDMA) wireless communication system generates and recovers spread-spectrum signals.
FIG. 1 is a block diagram of a two conventional channel cards of a first type.
A first channel card #0 of FIG. 1 includes a Digital Signal Processing (DSP) modem 100-1, a Field-Programmable Gate Array (FPGA) formatter 102-1, an Electrically Programmable Logic Device (EPLD) 104-1 and an oscillator (OSC) 106-1. A second channel card #1 of FIG. 1 includes a Digital Signal Processing (DSP) modem 100-2, a Field-Programmable Gate Array (FPGA) formatter 102-2, an Electrically Programmable Logic Device (EPLD) 104-2 and an oscillator (OSC) 106-2.
Each of the DSP modems 100-1 and 100-2 processes (e.g., OFDM modulates/demodulates or CDMA modulates/demodulates) digital data, acquired from an Analog-to-Digital (A/D) converter (not shown), through an algebraic operation. The DSP modems 100-1 and 100-2 operate respectively by receiving a DSP processing clock signal from oscillators (OSCs) 106-1 and 106-2, which may be 40 Mhz oscillators. The EPLDs 104-1 and 104-2 respectively issue a signal for controlling the FPGA formatters 102-1 and 102-2 and provide system clock signals, such as 80 ms/5 ms/50 Mhz clock signals, required for the operation of the FPGA formatters 102-1 and 102-2. The FPGA formatters 102-1 and 102-2 respectively match the signals of the DSP modems 100-1 and 100-2 and each send the matched signals to an InterFace (IF) board 110.
However, when the DSP modems 100-1 and 100-2 include only Digital Signal Processors (DSPs), as illustrated in FIG. 1, there is no interface to receive an interrupt for system clock (e.g., 80 ms and 5 ms) synchronization. Therefore, a specific protocol for the system synchronization is required.
FIG. 2 is a block diagram of a conventional channel card of a second type.
In the channel card of FIG. 2, a DSP modem 200 and an FPGA modem 202 process and generate data within the FPGA section. Thus, a protocol for a separate synchronization is unnecessary.
However, since the DSP modem 200 of the channel card of FIG. 2 operates by receiving a clock signal from the local oscillator 208, such as a 40 MHz oscillator, the data output timing may change with respect to the data synchronized to the 80 ms/5 ms/50 Mhz clock signals from the EPLD 206 every time the channel card is powered on/off. As a result, a problem may arise when the IF board combines the data output from different channel cards. In other words, when the FPGA formatter 204 receives the data from the DSP modem 200 as in the conventional channel card, the synchronization in the channel card or between the channel cards may differ because of the respective timing of DSP processing clock changing due to a power on/off. In addition, since the hardware of the conventional DSP modem cannot receive and process the system clock directly, synchronization with the system is infeasible.
Therefore, what is needed is an apparatus and a method for processing the synchronization of the DSP modem and the FPGA modem in the channel card, and the synchronization between the channel cards including the DSP modem and the FPGA modem.